This invention relates to a hybrid multiplex synchronizing method and an apparatus therefor. More particularly, the invention relates to a hybrid multiplex synchronizing method and apparatus in which a connection can freely be made to communication networks having different frame patterns and different frame lengths.
Data communication equipment is adapted to accept and process a number of items of frame data which arrive from a plurality of various nodes (data communication equipment) via a time-sharing multiplex communication line. Since each item of frame data arrives in a different phase, however, synchronizing processing must be executed in the receiving data communication equipment before the prescribed processing is executed.
In order to perform multiplex synchronizing processing, it is known to use a multiplex synchronizing processing apparatus which has a multiplex synchronizing processor 11 and a frame aligning RAM 12, as illustrated in FIG. 1. When one frame period T is partitioned into N (e.g., 64) time slots TS1.about.TS64, as illustrated in FIG. 2, time-shared multiplexed data of 64 channels allocated to respective ones of the time slot enter the multiplex synchronizing processor 11. Each item of time-shared multiplexed data is composed of eight bits, in which the first bit is a synchronizing bit (a frame bit), the eighth bit is a status bit (which indicates validity/invalidity), and the remaining bits are data. In a case where one frame has a period of 8K, the frame data (parallel data) has a speed of 512K. Furthermore, one sub-rate frame is composed of 20 frames.
In an ideal case in which synchronization has been achieved, as shown in FIG. 3 (where the frame length is assumed to be 20), the frame bit of all data in time slots TS1.about.TS64 in a first frame FP1 is S1, the frame bit of all data in time slots TS1.about.TS64 in a second frame FP2 is S2, the frame bit of all data in time slots TS1.about.TS64 in a third frame FP3 is S3, . . . , and the frame bit of all data in time slots TS1.about.TS64 in a 20th frame FP20 is S20. Furthermore, as shown in FIG. 4, a synchronization pattern (referred to as a frame pattern) of 20 bits synchronized to the sub-rate frame (which is equivalent to 20 frames) is constructed by lining up the 20 frame bits in the manner EQU S1, S2, S3, . . . , S20.
The multiplex synchronizing processor 11 (FIG. 1) rearranges the 20 frames of data (64 time slots.times.20 items of data), which are inputted in different phases, every time slot TS in the order of the frame bits and stores these data in the frame aligning RAM 12. For example, when the data of 64 time slots in each of frames FP1.about.FP20 enter in respectively different phases, as shown in FIG. 5A, these data are arranged by synchronizing processing in the frame aligning RAM 12, as shown in FIG. 5B, and the data eventually are rearranged and stored in the frame aligning RAM 12 as illustrated in FIG. 3. Thereafter, data of 64 time slots each are outputted every frame starting from the first frame of the frame aligning RAM 12.
More specifically, as depicted in FIG. 5B, the frame aligning RAM 12 has an address space composed of time-slot addresses (TS addresses) 1.about.64 of 64 time slots along the horizontal axis and sub-rate addresses 0.about.19 of 20 frames along the vertical axis. The multiplex synchronizing processor 11 identifies the frame-bit position of the inputted data in each time slot, subsequently outputs data of 64 time slots of the first frame bit S1 (namely data stored at sub-rate address 0, these data being indicated by the hatching), and then successively outputs the data of 64 time slots of the second frame bit S2, the data of 64 time slots of the second frame bit S3, . . . , and so on.
FIG. 6 illustrates the overall time chart of synchronizing processing and shows a frame synchronizing clock (512K), the data in each time slot, timing FAIN of data input to the frame aligning RAM, and timing FAOUT of data readout from the frame aligning RAM. The multiplex synchronizing processor 11 accepts the frame data, applies synchronizing processing and inputs the result to the frame aligning RAM 12 in the first half-period of the frame synchronizing clock, and reads the synchronized frame data out of the frame aligning RAM 12 and outputs the data in the second half-period of the frame synchronizing clock.
FIG. 7 is an overall view of the system in a single frame pattern network (an X.50 network, by way of example). Numerals 1.about.3 denote X.50 networks recommended by the CCITT, 4 a data multiplex communication apparatus, and PT1.about.PT3 time-sharing multiplex communication lines. In the data multiplex communication apparatus 4, numerals 4a.about.4c denote interface networks, 4d an internal bus, and 4e a multiplex synchronizing processing apparatus (see FIG. 1).
Time-shared multiplexed data strings TSD1.about.TSD3 of N channels (ch1.about.chN) per frame are inputted to the data multiplex communication apparatus 4 from the X.50 networks via the lines PT1.about.PT3, respectively. The numerals 1.about.20 in each of the time-shared multiplexed data strings TSD1.about.TSD3 indicate the positions of the respective frame bits EQU S1, S2, S3, . . . , S20.
It should be noted that, with regard to the same channel (time slot) of each frame in the time-shared multiplexed data strings, the frame bits are always arranged in the manner .fwdarw.S1.fwdarw.S2.fwdarw.S3.fwdarw. . . . S20.fwdarw.S1.fwdarw.S2.fwdarw. . . . in the order of arrival.
In the data multiplex communication apparatus 4, if the data of ch2 on line PT1, ch1 on line PT2, ch1 on line PT2, . . . are accepted and outputted upon being subjected to multiplex synchronizing processing, the data are successively extracted from each of the interfaces 4a.about.4c, arranged as shown in FIG. 8 and inputted to the multiplex synchronizing processing apparatus 4e. The frame patterns of the data allocated to the time slots TS1, TS2, TS3, . . . differ in phase in the manner
S19, S20, S1, . . .
S1, S2, S3, . . .
S7, S8, S9, . . .
Accordingly, through the method described in FIGS. 1 through 6, the multiplex synchronizing processing apparatus 4e aligns the phases of the frame patterns of the data allocated to the time slots.
In accordance with the conventional multiplex synchronizing method, as set forth above, if the data are data received from identical networks (e.g., X.50 networks) having the same frame pattern and the same frame length, the phases can be made to conform by synchronizing processing if the phases of the data differ.
With the conventional multiplex synchronizing method, however, the phases cannot be made to conform if the data are received in different phases from networks (multiplex networks) having different frame patterns and different frame lengths.
Consequently, it is necessary to newly and individually provide multiplex synchronizing processing apparatuses corresponding to the frame patterns and frame lengths which are specific to networks other than the X.50 networks. As a result, there is an increase in the amount of hardware and a flexible network configuration is not possible.